Numerous techniques have been used to isolate active devices (e.g. transistors, diodes) formed in a same semiconductor substrate. One technique is forming an active device in a well or tub which provides junction-isolation, whereby the well or tub is electrically isolated from adjacent areas by a reverse biased pn junction.
A very different type of isolation technique is to physically etch a trench in the semiconductor substrate, where this trench surrounds an active device. This trench isolation of an active device from other active devices outside the trench inherently results in a degree of electrical isolation between the active devices.
Trench isolation has been found advantageous in high density MOSFET applications, since these trenches can be predictably formed to submicron dimensions.
One problem which has been recognized in isolating MOS devices with trench isolation is the formation of a parasitic leakage path in a trench-isolated NMOS device due to the inversion of P-type trench sidewalls by positively charged contaminants in deposited oxide which fills the trenches. Deposited oxide is frequently contaminated with positive ions (such as sodium) which draw electrons in the P-type substrate to the P-type sidewalls of the trenches and thereby create an N-channel conducting path between the N-type source and drain regions of the NMOS transistor.
It is known to prevent this parasitic leakage path between the source and drain regions of an NMOS transistor by increasing the P-type doping concentration in the sidewalls of the trenches. Known techniques for doping the generally vertical sidewalls of the trenches include an angled field implant where P-type boron ions are implanted into the vertical trench-sidewalls at a large implantation tilt-angle. Such a process is described in the article entitled "A Practical Trench Isolation Technology with a Novel Planarization Process," by G. Fuse, et. al., IEDM 87.
Another method to dope the substantially vertical trench sidewalls is to deposit a P+ polysilicon or borosilicate glass (BSG) film into the trenches, where the boron in these films is then out-diffused into the sidewalls. This boron diffusion source may then be removed by a conventional etching process. The resulting P-type doping concentration in the sidewalls will thus prevent any parasitic leakage path between N-type source and drain regions along the sidewalls. Such a sidewall doping process using a deposited film is described in the article entitled "A Variable-Size Shallow Trench Isolation (STI) Technology with Diffused Sidewall Doping for Submicron CMOS," by B. Davari, IEDM 88.
Both the above doping techniques for the sidewalls of trenches have significant drawbacks. The tilted ion implantation technique described above produces nonuniform concentrations of dopants in the sidewalls of deep or narrow trenches, since the ion trajectories will be blocked by the surface of the wafer which surrounds the deep or narrow trenches. Further, in this tilted implantation process, opposing sidewall faces must be doped using opposite tilt angles, which requires shifting the angle of the ion beam relative to the wafer after one sidewall face is doped. The second method, using a deposited film as a P-type impurity diffusion source, requires additional and time-consuming steps to deposit the diffusion source, out-diffuse the impurities, and remove the diffusion source. Further, the resulting dopant concentration is difficult to accurately predict.
What is needed is a more reliable and faster method for etching trenches to isolate active devices and for doping the sidewalls of these trenches to prevent parasitic leakage currents between regions of an NMOS transistor.